A Phase-Locked Loop (PLL) may be used to generate an output signal having a desired frequency, such as a clock signal. A PLL might “lock” to the desired frequency by receiving its output signal via a feedback loop, determining a difference between the output signal and a reference signal, and changing its transfer function in order to reduce the difference.
PLL design often involves trade-offs between tuning range and noise immunity. More specifically, some conventional PLL designs provide a wide range of output frequencies while exhibiting poor noise immunity, while others provide a narrow range of output frequencies while exhibiting good noise immunity. PLL designs that may provide suitable response characteristics within a range of normal operating frequencies are desired.